Analysis of Multi-Layer Ceramic Capacitors
To evaluate capacitor modeling impact on PDN performance a test layout was realized. A 10-layer stack-up was chosen with the power net routed on layers 5 and 6, while the ground net on layers 4 and 7. Figure 9 highlights the power plane routing, location of the VRM, capacitors and the load IC, which is a processor with two internal Dual ARM logic cores.